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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>Contains generic APIs that are locally called or used within the HDMIPHY driver. </p>
<dl class="section note"><dt>Note</dt><dd>None.</dd></dl>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who  Date     Changes
</p>
<hr/>
<p>
           dd/mm/yy
</p>
<hr/>
<p>
1.0   gm   10/12/18 Initial release.
1.1   ku   17/05/20 Adding uniquification to avoid clash with vphy
1.1   ku   23/05/20 Corrected XHdmiphy1_Ch2Ids to set correct value
                    for Id1
</pre> </div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga70ecb3c5614ea8c97c0bc56bd395ac2c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga70ecb3c5614ea8c97c0bc56bd395ac2c">XHdmiphy1_Ch2Ids</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u8 *Id0, u8 *Id1)</td></tr>
<tr class="memdesc:ga70ecb3c5614ea8c97c0bc56bd395ac2c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will set the channel IDs to correspond with the supplied channel ID based on the protocol.  <a href="group__xhdmiphy1.html#ga70ecb3c5614ea8c97c0bc56bd395ac2c">More...</a><br/></td></tr>
<tr class="separator:ga70ecb3c5614ea8c97c0bc56bd395ac2c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacfaf4756f5682dfda2739a8083deea56"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gacfaf4756f5682dfda2739a8083deea56">XHdmiphy1_DirReconfig</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, XHdmiphy1_DirectionType Dir)</td></tr>
<tr class="memdesc:gacfaf4756f5682dfda2739a8083deea56"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will set the current RX/TX configuration over DRP.  <a href="group__xhdmiphy1.html#gacfaf4756f5682dfda2739a8083deea56">More...</a><br/></td></tr>
<tr class="separator:gacfaf4756f5682dfda2739a8083deea56"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0fa2836b8aac17e187bf1e01a462001a"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga0fa2836b8aac17e187bf1e01a462001a">XHdmiphy1_WriteCfgRefClkSelReg</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId)</td></tr>
<tr class="memdesc:ga0fa2836b8aac17e187bf1e01a462001a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function writes the current software configuration for the reference clock selections to hardware for the specified quad on all channels.  <a href="group__xhdmiphy1.html#ga0fa2836b8aac17e187bf1e01a462001a">More...</a><br/></td></tr>
<tr class="separator:ga0fa2836b8aac17e187bf1e01a462001a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf3cb368774462d22b085a8e34d2c7a00"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gaf3cb368774462d22b085a8e34d2c7a00">XHdmiphy1_CfgPllRefClkSel</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, <a class="el" href="group__xhdmiphy1.html#gaec55cf3dfcfa0c7cf9749c63690dd019">XHdmiphy1_PllRefClkSelType</a> RefClkSel)</td></tr>
<tr class="memdesc:gaf3cb368774462d22b085a8e34d2c7a00"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configure the PLL reference clock selection for the specified channel(s).  <a href="group__xhdmiphy1.html#gaf3cb368774462d22b085a8e34d2c7a00">More...</a><br/></td></tr>
<tr class="separator:gaf3cb368774462d22b085a8e34d2c7a00"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4e6b72ef1579950b4c8c83e35e7ad4b0"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga4e6b72ef1579950b4c8c83e35e7ad4b0">XHdmiphy1_CfgSysClkDataSel</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, <a class="el" href="group__xhdmiphy1.html#ga4d998790546ec3dde5119376868686e6">XHdmiphy1_SysClkDataSelType</a> SysClkDataSel)</td></tr>
<tr class="memdesc:ga4e6b72ef1579950b4c8c83e35e7ad4b0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configure the SYSCLKDATA reference clock selection for the direction.  <a href="group__xhdmiphy1.html#ga4e6b72ef1579950b4c8c83e35e7ad4b0">More...</a><br/></td></tr>
<tr class="separator:ga4e6b72ef1579950b4c8c83e35e7ad4b0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga738210e1c11e69176f1cd733ff0bae6c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga738210e1c11e69176f1cd733ff0bae6c">XHdmiphy1_CfgSysClkOutSel</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, <a class="el" href="group__xhdmiphy1.html#gac87909fabb3f765c0be156e7082aea8e">XHdmiphy1_SysClkOutSelType</a> SysClkOutSel)</td></tr>
<tr class="memdesc:ga738210e1c11e69176f1cd733ff0bae6c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configure the SYSCLKOUT reference clock selection for the direction.  <a href="group__xhdmiphy1.html#ga738210e1c11e69176f1cd733ff0bae6c">More...</a><br/></td></tr>
<tr class="separator:ga738210e1c11e69176f1cd733ff0bae6c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf524ddfb56aa7742cf9c7fc777a2273a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gaf524ddfb56aa7742cf9c7fc777a2273a">XHdmiphy1_GetRcfgChId</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, <a class="el" href="group__xhdmiphy1.html#gae8559ee2ca7c404467a72f4653a5d4f5">XHdmiphy1_PllType</a> PllType)</td></tr>
<tr class="memdesc:gaf524ddfb56aa7742cf9c7fc777a2273a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Obtain the reconfiguration channel ID for given PLL type.  <a href="group__xhdmiphy1.html#gaf524ddfb56aa7742cf9c7fc777a2273a">More...</a><br/></td></tr>
<tr class="separator:gaf524ddfb56aa7742cf9c7fc777a2273a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac05b90ab984e726f1ddde5cf265915d9"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gac05b90ab984e726f1ddde5cf265915d9">XHdmiphy1_IsPllLocked</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId)</td></tr>
<tr class="memdesc:gac05b90ab984e726f1ddde5cf265915d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will check the status of a PLL lock on the specified channel.  <a href="group__xhdmiphy1.html#gac05b90ab984e726f1ddde5cf265915d9">More...</a><br/></td></tr>
<tr class="separator:gac05b90ab984e726f1ddde5cf265915d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaa8cf29813f43a1066492adea335bf48"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gaaa8cf29813f43a1066492adea335bf48">XHdmiphy1_GetQuadRefClkFreq</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#gaec55cf3dfcfa0c7cf9749c63690dd019">XHdmiphy1_PllRefClkSelType</a> RefClkType)</td></tr>
<tr class="memdesc:gaaa8cf29813f43a1066492adea335bf48"><td class="mdescLeft">&#160;</td><td class="mdescRight">Obtain the current reference clock frequency for the quad based on the reference clock type.  <a href="group__xhdmiphy1.html#gaaa8cf29813f43a1066492adea335bf48">More...</a><br/></td></tr>
<tr class="separator:gaaa8cf29813f43a1066492adea335bf48"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa91560e5b99db9d90042b548a76da7a6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#ga4d998790546ec3dde5119376868686e6">XHdmiphy1_SysClkDataSelType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gaa91560e5b99db9d90042b548a76da7a6">XHdmiphy1_GetSysClkDataSel</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId)</td></tr>
<tr class="memdesc:gaa91560e5b99db9d90042b548a76da7a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Obtain the current [RT]XSYSCLKSEL[0] configuration.  <a href="group__xhdmiphy1.html#gaa91560e5b99db9d90042b548a76da7a6">More...</a><br/></td></tr>
<tr class="separator:gaa91560e5b99db9d90042b548a76da7a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabf0e7c8a542401ba275640fabee19940"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#gac87909fabb3f765c0be156e7082aea8e">XHdmiphy1_SysClkOutSelType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gabf0e7c8a542401ba275640fabee19940">XHdmiphy1_GetSysClkOutSel</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId)</td></tr>
<tr class="memdesc:gabf0e7c8a542401ba275640fabee19940"><td class="mdescLeft">&#160;</td><td class="mdescRight">Obtain the current [RT]XSYSCLKSEL[1] configuration.  <a href="group__xhdmiphy1.html#gabf0e7c8a542401ba275640fabee19940">More...</a><br/></td></tr>
<tr class="separator:gabf0e7c8a542401ba275640fabee19940"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaff834a7a15854c09af35144299a4f980"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gaff834a7a15854c09af35144299a4f980">XHdmiphy1_GtUserRdyEnable</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, XHdmiphy1_DirectionType Dir, u8 Hold)</td></tr>
<tr class="memdesc:gaff834a7a15854c09af35144299a4f980"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will reset and enable the Video PHY's user core logic.  <a href="group__xhdmiphy1.html#gaff834a7a15854c09af35144299a4f980">More...</a><br/></td></tr>
<tr class="separator:gaff834a7a15854c09af35144299a4f980"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga47707c2203c7788afdfb22fe1ae438db"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga47707c2203c7788afdfb22fe1ae438db">XHdmiphy1_MmcmReset</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u8 Hold)</td></tr>
<tr class="memdesc:ga47707c2203c7788afdfb22fe1ae438db"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will reset the mixed-mode clock manager (MMCM) core.  <a href="group__xhdmiphy1.html#ga47707c2203c7788afdfb22fe1ae438db">More...</a><br/></td></tr>
<tr class="separator:ga47707c2203c7788afdfb22fe1ae438db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6d652ca1a4650bc5a2762d381a110f6b"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga6d652ca1a4650bc5a2762d381a110f6b">XHdmiphy1_MmcmLockedMaskEnable</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u8 Enable)</td></tr>
<tr class="memdesc:ga6d652ca1a4650bc5a2762d381a110f6b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will reset the mixed-mode clock manager (MMCM) core.  <a href="group__xhdmiphy1.html#ga6d652ca1a4650bc5a2762d381a110f6b">More...</a><br/></td></tr>
<tr class="separator:ga6d652ca1a4650bc5a2762d381a110f6b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0b46b7c2c9c6d5fbe7e7c2a6d226b985"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga0b46b7c2c9c6d5fbe7e7c2a6d226b985">XHdmiphy1_MmcmLocked</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir)</td></tr>
<tr class="memdesc:ga0b46b7c2c9c6d5fbe7e7c2a6d226b985"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will get the lock status of the mixed-mode clock manager (MMCM) core.  <a href="group__xhdmiphy1.html#ga0b46b7c2c9c6d5fbe7e7c2a6d226b985">More...</a><br/></td></tr>
<tr class="separator:ga0b46b7c2c9c6d5fbe7e7c2a6d226b985"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2b93ca125219d62f19817168267ddfc5"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga2b93ca125219d62f19817168267ddfc5">XHdmiphy1_MmcmSetClkinsel</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, XHdmiphy1_MmcmClkinsel Sel)</td></tr>
<tr class="memdesc:ga2b93ca125219d62f19817168267ddfc5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will set the CLKINSEL port of the MMCM.  <a href="group__xhdmiphy1.html#ga2b93ca125219d62f19817168267ddfc5">More...</a><br/></td></tr>
<tr class="separator:ga2b93ca125219d62f19817168267ddfc5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafb115f999643adac66932d6c4a44de1c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gafb115f999643adac66932d6c4a44de1c">XHdmiphy1_SetBufgGtDiv</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, XHdmiphy1_DirectionType Dir, u8 Div)</td></tr>
<tr class="memdesc:gafb115f999643adac66932d6c4a44de1c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function obtains the divider value of the BUFG_GT peripheral.  <a href="group__xhdmiphy1.html#gafb115f999643adac66932d6c4a44de1c">More...</a><br/></td></tr>
<tr class="separator:gafb115f999643adac66932d6c4a44de1c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf1fbb7de9d26abab7332a62932be9d85"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gaf1fbb7de9d26abab7332a62932be9d85">XHdmiphy1_PowerDownGtPll</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u8 Hold)</td></tr>
<tr class="memdesc:gaf1fbb7de9d26abab7332a62932be9d85"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will power down the specified GT PLL.  <a href="group__xhdmiphy1.html#gaf1fbb7de9d26abab7332a62932be9d85">More...</a><br/></td></tr>
<tr class="separator:gaf1fbb7de9d26abab7332a62932be9d85"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad8f3d6250fe7c2d7384a5f20507da509"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gad8f3d6250fe7c2d7384a5f20507da509">XHdmiphy1_ClkCalcParams</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, XHdmiphy1_DirectionType Dir, u32 PllClkInFreqHz)</td></tr>
<tr class="memdesc:gad8f3d6250fe7c2d7384a5f20507da509"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will try to find the necessary PLL divisor values to produce the configured line rate given the specified PLL input frequency.  <a href="group__xhdmiphy1.html#gad8f3d6250fe7c2d7384a5f20507da509">More...</a><br/></td></tr>
<tr class="separator:gad8f3d6250fe7c2d7384a5f20507da509"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga03e2d2bdcf56e256ff08f5776313a76e"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga03e2d2bdcf56e256ff08f5776313a76e">XHdmiphy1_OutDivReconfig</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, XHdmiphy1_DirectionType Dir)</td></tr>
<tr class="memdesc:ga03e2d2bdcf56e256ff08f5776313a76e"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will set the current output divider configuration over DRP.  <a href="group__xhdmiphy1.html#ga03e2d2bdcf56e256ff08f5776313a76e">More...</a><br/></td></tr>
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<tr class="memitem:gaeb31d823a71bad5b0bb6250b016577d7"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gaeb31d823a71bad5b0bb6250b016577d7">XHdmiphy1_ClkReconfig</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId)</td></tr>
<tr class="memdesc:gaeb31d823a71bad5b0bb6250b016577d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will set the current clocking settings for each channel to hardware based on the configuration stored in the driver's instance.  <a href="group__xhdmiphy1.html#gaeb31d823a71bad5b0bb6250b016577d7">More...</a><br/></td></tr>
<tr class="separator:gaeb31d823a71bad5b0bb6250b016577d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga27c96bba79f91125a226948b139fe9d3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#ga4d998790546ec3dde5119376868686e6">XHdmiphy1_SysClkDataSelType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga27c96bba79f91125a226948b139fe9d3">XHdmiphy1_Pll2SysClkData</a> (<a class="el" href="group__xhdmiphy1.html#gae8559ee2ca7c404467a72f4653a5d4f5">XHdmiphy1_PllType</a> PllSelect)</td></tr>
<tr class="memdesc:ga27c96bba79f91125a226948b139fe9d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will translate from XHdmiphy1_PllType to XHdmiphy1_SysClkDataSelType.  <a href="group__xhdmiphy1.html#ga27c96bba79f91125a226948b139fe9d3">More...</a><br/></td></tr>
<tr class="separator:ga27c96bba79f91125a226948b139fe9d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad369e0c6d06d2f66606c845b3976fe75"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#gac87909fabb3f765c0be156e7082aea8e">XHdmiphy1_SysClkOutSelType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gad369e0c6d06d2f66606c845b3976fe75">XHdmiphy1_Pll2SysClkOut</a> (<a class="el" href="group__xhdmiphy1.html#gae8559ee2ca7c404467a72f4653a5d4f5">XHdmiphy1_PllType</a> PllSelect)</td></tr>
<tr class="memdesc:gad369e0c6d06d2f66606c845b3976fe75"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will translate from XHdmiphy1_PllType to XHdmiphy1_SysClkOutSelType.  <a href="group__xhdmiphy1.html#gad369e0c6d06d2f66606c845b3976fe75">More...</a><br/></td></tr>
<tr class="separator:gad369e0c6d06d2f66606c845b3976fe75"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga87f9523a81f1b648cfae0172bdd96f0b"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga87f9523a81f1b648cfae0172bdd96f0b">XHdmiphy1_PllCalculator</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, XHdmiphy1_DirectionType Dir, u32 PllClkInFreqHz)</td></tr>
<tr class="memdesc:ga87f9523a81f1b648cfae0172bdd96f0b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will try to find the necessary PLL divisor values to produce the configured line rate given the specified PLL input frequency.  <a href="group__xhdmiphy1.html#ga87f9523a81f1b648cfae0172bdd96f0b">More...</a><br/></td></tr>
<tr class="separator:ga87f9523a81f1b648cfae0172bdd96f0b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7cd4d4f88631190ea51009300a15b783"><td class="memItemLeft" align="right" valign="top">u64&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga7cd4d4f88631190ea51009300a15b783">XHdmiphy1_GetPllVcoFreqHz</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, XHdmiphy1_DirectionType Dir)</td></tr>
<tr class="memdesc:ga7cd4d4f88631190ea51009300a15b783"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function calculates the PLL VCO operating frequency.  <a href="group__xhdmiphy1.html#ga7cd4d4f88631190ea51009300a15b783">More...</a><br/></td></tr>
<tr class="separator:ga7cd4d4f88631190ea51009300a15b783"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga22de3338657208e2ee991d68f0248195"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga22de3338657208e2ee991d68f0248195">XHdmiphy1_GetRefClkSourcesCount</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga22de3338657208e2ee991d68f0248195"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns the number of active reference clock sources based in the CFG.  <a href="group__xhdmiphy1.html#ga22de3338657208e2ee991d68f0248195">More...</a><br/></td></tr>
<tr class="separator:ga22de3338657208e2ee991d68f0248195"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab75f3892f884d01f855d607291eba269"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gab75f3892f884d01f855d607291eba269">XHdmiphy1_IsHDMI</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, XHdmiphy1_DirectionType Dir)</td></tr>
<tr class="memdesc:gab75f3892f884d01f855d607291eba269"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function checks if Instance is HDMI 2.0 or HDMI 2.1.  <a href="group__xhdmiphy1.html#gab75f3892f884d01f855d607291eba269">More...</a><br/></td></tr>
<tr class="separator:gab75f3892f884d01f855d607291eba269"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3fc9cb2326efad44689d4af163343b7f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga3fc9cb2326efad44689d4af163343b7f">XHdmiphy1_ErrorHandler</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga3fc9cb2326efad44689d4af163343b7f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is the error condition handler.  <a href="group__xhdmiphy1.html#ga3fc9cb2326efad44689d4af163343b7f">More...</a><br/></td></tr>
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